Programmable Array Logic - PDFSEARCH.IO - Document Search Engine

Programmable Array Logic
Results: 262

#	Item
111	Benchmarking Method and Designs Targeting Logic Synthesis for FPGAs Joachim Pistorius, Mike Hutton Altera Corp. 101 Innovation Drive San Jose, CA 95134 {jpistori,mhutton}@altera.com Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2007-04-20 22:36:42 Logic synthesis Physical design Register-transfer level Altera Quartus Place and route Application-specific integrated circuit Integrated circuit design Digital electronics Semiconductor intellectual property core Electronic engineering Electronic design automation Field-programmable gate array
112	Generating Efficient Libraries for use in FPGA Resynthesis Algorithms Andrew Kennings Alan Mishchenko Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2010-03-10 22:06:40 Digital electronics Boolean algebra Arrays Computer performance Lookup table Field-programmable gate array Truth table Programmable logic device Function Mathematics Electronic engineering Computing
113	Microsoft Word - power18.doc Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2009-07-10 18:57:40 Electronic design Integrated circuits And-inverter graph Field-programmable gate array Logic synthesis Logic gate Sequential logic Power optimization CMOS Electronic engineering Electronic design automation Digital electronics
114	Integrating Logic Synthesis, Technology Mapping, and Retiming Alan Mishchenko Satrajit Chatterjee Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-05-01 16:05:11 Digital electronics Electronic design Formal methods And-inverter graph Retiming Logic synthesis Automatic test pattern generation Field-programmable gate array Sequential logic Electronic engineering Electronics Electronic design automation
115	Board-Level Multiterminal Net Assignment Xiaoyu Song1, William N. N. Hung2, Alan Mishchenko1, Malgorzata Chrzanowska-Jeske1, Alan Coppola3 and Andrew Kennings4 1 Department of ECE, Portland State University, Portland, O Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2002-03-01 13:11:46 Applied mathematics Logic in computer science NP-complete problems Formal methods Boolean algebra Boolean satisfiability problem Field-programmable gate array Conjunctive normal form Routing Theoretical computer science Electronic engineering Electronic design automation
116	Improvements to Technology Mapping for LUT-Based FPGAs Alan Mishchenko Satrajit Chatterjee Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-02-27 22:53:37 Diagrams And-inverter graph Logic synthesis Field-programmable gate array Directed acyclic graph Algorithm Heuristic function Electronic engineering Electronic design automation Electrical engineering
117	DAG-Aware AIG Rewriting A Fresh Look at Combinational Logic Synthesis Alan Mishchenko Satrajit Chatterjee Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-05-08 11:02:22 Digital electronics Electronic design Logic in computer science And-inverter graph Logic synthesis Field-programmable gate array American International Group Directed acyclic graph Logic gate Electronic engineering Electronic design automation Formal methods
118	Microsoft Word - fpga061s-mishchenko1.doc Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2009-12-16 19:04:56 Digital electronics Electronic design And-inverter graph Field-programmable gate array Logic synthesis Static timing analysis Placement Logic optimization Propagation delay Electronic engineering Electronic design automation Formal methods
119	SynaptiCAD Big Feature List SynaptiCAD was founded in 1992 to provide affordable high quality timing diagram editing tools. Since that time we have expanded our product line to include: VHDL & Verilog test bench generati Add to Reading List Source URL: www.syncad.com Language: English - Date: 2011-04-06 10:25:45 Verilog VHDL Waveform viewer Logic analyzer Field-programmable gate array Jitter Aldec Phase-locked loop Static timing analysis Electronic engineering Electronics Hardware description languages
120	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 3, JUNE[removed]Transactions Briefs__________________________________________________________________ Board-Level Multiterminal Net Assignm Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2003-07-31 11:09:07 Logic in computer science NP-complete problems Electronic design automation Formal methods Boolean algebra Boolean satisfiability problem Field-programmable gate array MOS Technology SID Hardware emulation Theoretical computer science Electronic engineering Applied mathematics